TSMC and Winbond build localized 3D DRAM stacking to cut supply-chain risk
In brief
- TSMC and Winbond collaborate on 3D wafer-on-wafer DRAM stacking using Winbond's CUBE architecture
- Winbond's CUBE delivers scalable memory densities from 256Mb to 8Gb per die
- TSMC's Parts Localization Program generated NT$2 billion output value and cut validation times 50%
Building local memory capacity
TSMC and Winbond are collaborating on a localized DRAM supply chain using 3D wafer-on-wafer stacking technology. Winbond supplies specialized DRAM wafers designed for next-generation WoW stacking processes. Its proprietary architecture, called CUBE (Customized Ultra-Bandwidth Elements), is purpose-built for this kind of integration.
CUBE offers scalable memory options with densities ranging from 256Mb to 8Gb per die. TSMC handles the stacking and integration through its existing SoIC/WoW packaging capabilities. The two companies are targeting edge AI workloads and other applications that benefit from tightly integrated memory.
Supply-chain autonomy and scale
Most high-bandwidth memory used in AI training today comes from Samsung and SK Hynix in South Korea. By developing an alternative pathway within Taiwan, the partnership addresses a strategic gap — not all memory needs require the highest-end HBM, and localized production can reduce lead times and geopolitical risk for certain use cases.
TSMC's Parts Localization Program, initiated in 2024, has contributed over NT$2 billion (roughly $62 million) in annual output value as of February 2026. The program also reduced validation times by approximately 50% in the same period. This infrastructure supports the Winbond collaboration and other efforts to strengthen Taiwan's semiconductor ecosystem.
What's not yet public
Neither TSMC nor Winbond has publicly disclosed yield data or production timelines for this specific collaboration. UMC, Taiwan's second-largest foundry, publicly announced its own wafer-to-wafer 3D IC initiative involving Winbond and other partners on October 31, 2023. The broader trend suggests Taiwan's chipmakers are moving in parallel to reduce memory supply-chain concentration.
